1. Technical Field
The present invention relates to a data processing system that has a function for reducing power consumption.
2. Description of the Related Art
The ability of mobile appliances, such as mobile phones and mobile terminals, have been greatly expanded together with the advances in information, communication and network technologies. Mobile appliances are assumed to operate on batteries, so that there are stringent demands for the LSIs (Large Scale Integrated circuits) that are central to the constructions of such systems to operate with low power consumption. Japanese Laid-Open Patent Application No. 2000-112585 discloses a technique where power consumption is reduced in a system LSI, which includes one or a plurality of hardware modules and a CPU that controls the operation of such hardware modules in accordance with a program, by executing sleep instructions for halting the supply of a clock to the CPU.
Since offchip capacitance is much higher than onchip capacitance, integrating functions that are distributed among a plurality of chips into a single chip as a system LSI has many benefits with regard to reducing power consumption. Also, a further reduction can be made in power consumption by dividing the plurality of functions that have been incorporated in a system LSI into blocks and controlling the clock signals supplied to such blocks separately for each functional block including CPU. However, CPU is the processor core and if the processor core is halted unnecessarily, this can cause a large drop in the performance of the system LSI, though if the processor core is not halted, less of a reduction is made in the power consumption. If a hard ware control is applied for judging conditions of the processor core and for realizing a halt state of the processor core, more area is required in LSI for such hardware and it is thought that power consumption will increase. When control is performed by software alone, there is the problem that it is difficult to estimate the period for which the processor core can be halted.
In Japanese Laid-Open Patent Application No. 2000-112585, the above problem is solved by halting the supply of the clock to the CPU using a sleep instruction and recommencing the supply of the clock to the CPU on receiving an end of processing by the hardware module. However, it is necessary to arrange sleep instructions for stopping the supply of the clock to the CPU in the program, so that in order to stop the supply of the clock to the CPU with appropriate timing, program developers have to examine all of the operations of the CPU, which is to say, the operations of the LSI. Such operations include conditional branches and interrupt processing, so that an extremely large amount of time and cost are required in order to develop a program where the CPU is stopped with the appropriate timing and only the appropriate periods.
During the development of a system LSI also, there are always modification and/or changes in response to changes in specification and version upgrades. Accordingly, it is almost impossible to develop programs so that the CPU is appropriately stopped in accordance with such changes. When an LSI with a different specification is developed, developing a program where the CPU is appropriately stopped causes delays in the development of the LSI, which does not suit the current development environment for system LSIs which requires LSIs to be put on the market within a short time. Accordingly, it can be said that at present, there is no applicable technology for providing system LSIs that can reduce power consumption by stopping the clock of a CPU that is the processor core or LSI.